Logic Gates as Repeaters (LGR) for area-efficient timing optimization
- Michael Moreinis
- Arkadiy Morgenshtein
- et al.
- 2006
- IEEE Transactions on VLSI Systems
Publications
Date
Featured collections
Popular topics
74 results at IEEE Transactions on VLSI Systems
A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies
- Jae-Joon Kim
- Kaushik Roy
- 2006
- IEEE Transactions on VLSI Systems
An asynchronous architecture for modeling intersegmental neural communication
- Girish N. Patel
- Michael S. Reid
- et al.
- 2006
- IEEE Transactions on VLSI Systems
Fast comparisons of circuit implementations
- Shrirang K. Karandikar
- Sachin S. Sapatnekar
- 2005
- IEEE Transactions on VLSI Systems
Combined circuit and architectural level variable supply-voltage scaling for low power
- Hai Li
- Chen-Yong Cher
- et al.
- 2005
- IEEE Transactions on VLSI Systems
A forward body-biased low-leakage SRAM cache: Device, circuit and architecture considerations
- Chris Hyung-Il Kim
- Jae-Joon Kim
- et al.
- 2005
- IEEE Transactions on VLSI Systems
Interpretation of Rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models
- Mary Yvonne Lanzerotti
- Giovanni Fiorenza
- et al.
- 2004
- IEEE Transactions on VLSI Systems
Assessment of on-chip wire-length distribution models
- Mary Y. Lanzerotti
- Giovanni Fiorenza
- et al.
- 2004
- IEEE Transactions on VLSI Systems
Critical evaluation of SOI design guidelines
- Rouwaida Kanj
- Elyse Rosenbaum
- 2004
- IEEE Transactions on VLSI Systems
A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture
- Sumio Morioka
- Akashi Satoh
- 2004
- IEEE Transactions on VLSI Systems