Hole mobility improvement in silicon-on-insulator and bulk silicon transistors using local strain
- S. Tiwari
- M.V. Fischetti
- et al.
- 1997
- IEDM 1997
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11 results at IEDM 1997
7.9/5.5 psec room/low temperature SOI CMOS
- F. Assaderaghi
- W. Rausch
- et al.
- 1997
- IEDM 1997
Full copper wiring in a sub-0.25 μm CMOS ULSI technology
- D. Edelstein
- J. Heidenreich
- et al.
- 1997
- IEDM 1997
0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
- D. Schepis
- F. Assaderaghi
- et al.
- 1997
- IEDM 1997
Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substrates
- L.K. Han
- S.W. Crowder
- et al.
- 1997
- IEDM 1997
Trade-offs in the integration of high performance devices with trench capacitor DRAM
- S.W. Crowder
- S. Stiffler
- et al.
- 1997
- IEDM 1997
Novel substrate contact structure for high-Q silicon-integrated spiral inductors
- J.N. Burghartz
- A.E. Ruehli
- et al.
- 1997
- IEDM 1997
Monte Carlo study of velocity overshoot in switching a 0.1-micron CMOS inverter
- S.E. Laux
- M.V. Fischetti
- 1997
- IEDM 1997
CMOS devices below 0.1 μm: How high will performance go?
- Yuan Taut
- E. Nowak
- 1997
- IEDM 1997
Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
- H.-S. Wong
- K.K. Chan
- et al.
- 1997
- IEDM 1997