Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies
- Rahul M. Rao
- Jeffrey L. Burns
- et al.
- 2003
- ESSCIRC 2003
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4 results at ESSCIRC 2003
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology
- Koushik K. Das
- Rajiv V. Joshi
- et al.
- 2003
- ESSCIRC 2003
Minimizing inductive noise in system-on-a-chip with multiple power gating structures
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2003
- ESSCIRC 2003
A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology
- Jean-Olivier Plouchart
- Jonghae Kim
- et al.
- 2003
- ESSCIRC 2003