Graphene nanostructures for device applications
- Joerg Appenzeller
- Yang Sui
- et al.
- 2009
- VLSI Technology 2009
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12 results at VLSI Technology 2009
Device technology innovation for exascale computing
- Tze-Chiang Chen
- 2009
- VLSI Technology 2009
Gate modulation of graphene contacts - On the scaling of graphene FETs
- Zhihong Chen
- Joerg Appenzeller
- 2009
- VLSI Technology 2009
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- VLSI Technology 2009
pFET V t control with HfO 2/TiN/poly-Si gate stack using a lateral oxygenation process
- B. Cartier
- M. Steen
- et al.
- 2009
- VLSI Technology 2009
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond
- K. Choi
- H. Jagannathan
- et al.
- 2009
- VLSI Technology 2009
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm
- N. Tega
- H. Miki
- et al.
- 2009
- VLSI Technology 2009
Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding
- R.R. Yu
- F. Liu
- et al.
- 2009
- VLSI Technology 2009