Level-shifted and voltage-reduced 0.5 μm BiCMOS circuits
- Chih-Liang Chen
- 1990
- ISSCC 1990
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2 results at ISSCC 1990
An 18 ns 56-bit multiply-adder circuit
- Robert K. Montoye
- P.W. Cook
- et al.
- 1990
- ISSCC 1990