Publication
ISSCC 1990
Conference paper

Level-shifted and voltage-reduced 0.5 μm BiCMOS circuits

Abstract

5-V BiCMOS digital circuits can provide significant speed improvement over CMOS circuits when driving heavy capacitance loads. The most commonly used 5-V BiCMOS circuit is the partial-swing circuit, which has 2-Vbe reduction of its output swing. The Vbe losses reduce both the noise margin and the overdrive voltage to the driven circuits. Owing to nonscaling of the bipolar Vbe, the effect becomes more severe as power supply is reduced. This partial-swing BiCMOS circuit has limited speed improvement over a 3.3-V conventional 0.5-μm CMOS circuit when implemented in a scaled-down 0.5-μm, 3.3-V BiCMOS technology. The concept of level-shifting a BiCMOS circuit is shown. The Vh and Vl supply rails for CMOS circuits are offset by Vbe (≅0.8 V) from the Vdd and Vss supplies, respectively. After a Vbe reduction similar to that in a partial-swing circuit, the output swing of the BiCMOS circuit matches the CMOS supply levels. Thus, CMOS-like noise margin and overdrive voltage can be achieved. The Vbe shift can be implemented simply by an NPN transistor connected as a diode, or by more complex voltage-regulator circuitry. For a single 5-V Vdd supply and grounded Vss, the Vh and Vl for CMOS circuits are about 4.2 V and 0.8 V, respectively. The net voltage across CMOS circuits is then (Vh-Vl), i.e., 3.4 V, which is close to a 3.3-V scaled-down supply for 0.5-μm CMOS devices.

Date

Publication

ISSCC 1990

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