A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2016
- ISSCC 2016
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4 results at ISSCC 2016
A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
- 2016
- ISSCC 2016
A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications
- Win-San Khwa
- Meng-Fan Chang
- et al.
- 2016
- ISSCC 2016
A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
- Sergey V. Rylov
- Troy Beukema
- et al.
- 2016
- ISSCC 2016