Challenges of cell selection algorithms in industrial high performance microprocessor designs
- Tiago J. Reimann
- Cliff Sze
- et al.
- 2016
- Integration, the VLSI Journal
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23 results at Integration, the VLSI Journal
ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS
- Akashi Satoh
- Tadanobu Inoue
- 2007
- Integration, the VLSI Journal
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
- Phillip Chin
- Charles A. Zukowski
- et al.
- 2005
- Integration, the VLSI Journal
Combinatorial cell design for CMOS libraries
- Frederik Beeftink
- Prabhakar Kudva
- et al.
- 2000
- Integration, the VLSI Journal
Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay
- S. Ramanathan
- V. Visvanathan
- 1999
- Integration, the VLSI Journal
FTROM: A Silicon Compiler for Fault-tolerant ROMs
- Anurag Gupta
- Kanad Chakraborty
- et al.
- 1998
- Integration, the VLSI Journal
On the optimal four-way switch box routing structures of FPGA greedy routing architectures
- Jiaofeng Pan
- Yu-Liang Wu
- et al.
- 1998
- Integration, the VLSI Journal
High-level synthesis techniques for functional test pattern execution
- Inki Hong
- Darko Kirovski
- et al.
- 1998
- Integration, the VLSI Journal
A backtracing-oriented procedure for the analysis of combinational gate-level designs
- Gabriel M. Silberman
- Ilan Y. Spillinger
- 1994
- Integration, the VLSI Journal
Data path synthesis
- Leon Stok
- 1994
- Integration, the VLSI Journal