Hasan M Nayfeh

Title

Senior Research Engineer, Quantum Computing

Bio

Extensive experience in semiconductor device design in support of nanoscale CMOS technology and superconducting qubit devices for quantum computing application. Received Ph.D. degree from MIT in EECS with thesis on strained silicon device scaling. Published > 30 journal papers and awarded 9 U.S. patents with citations > 2000. Recipient of two IBM’s Outstanding Technical Achievement Awards: (1) contributions to scaling up client accessible quantum computing systems with cutting-edge performance, and (2) Two-level system monitoring and mitigation of deployed systems

Publications

Channel strain engineering for high performance CMOS technology
- - Hasan M. Nayfeh
- 2008
- RTP 2008
(110) Channel, SiON gate-dielectric PMOS with record high I_on=1 mA/μm through channel stress and source drain external resistance (R _ext) engineering
- - B. Yang
  - A. Waite
  - et al.
- 2007
- IEDM 2007
Hole transport in nanoscale p-type MOSFET SOI devices with high strain
- - H. Nayfeh
  - S.-J. Jeng
  - et al.
- 2007
- DRC 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- - S. Narasimha
  - K. Onishi
  - et al.
- 2006
- IEDM 2006
Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
- - H. Nayfeh
  - D. Singh
  - et al.
- 2006
- IEEE Electron Device Letters
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- - W.-H. Lee
  - A. Waite
  - et al.
- 2005
- IEDM 2005
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- - D. Singh
  - J. Hergenrother
  - et al.
- 2005
- IEEE International SOI Conference 2005
Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakage
- - E. Gusev
  - C. Cabral Jr.
  - et al.
- 2004
- IEDM 2004
Impact of ion implantation damage and thermal budget on mobility enhancement in strained-Si N-channel MOSFETs
- - Guangrui Xia
  - Hasan M. Nayfeh
  - et al.
- 2004
- IEEE Transactions on Electron Devices
Investigation of Scaling Methodology for Strained Si n-MOSFETs Using a Calibrated Transport Model
- - Hasan M. Nayfeh
  - Judy L. Hoyt
  - et al.
- 2003
- IEDM 2003

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Patents

- 17 Jun 2014
- US
- 8754446
Semiconductor Structure And Method Of Making Same
- 03 Jun 2014
- US
- 8741725
Butted Soi Junction Isolation Structures And Devices And Method Of Fabrication
- 04 Feb 2014
- US
- 8642424
Replacement Metal Gate Structure And Methods Of Manufacture
- 12 Nov 2013
- GB
- 2497259
Fast - Butted Soi Junction Isolation Structures And Devices And Method Of Fabrication
- 31 Jul 2013
- CN
- ZL201010212242.9
Method Of Creating Asymmetric Field-effect-transistors
- 09 Jul 2013
- US
- 8482075
Structure And Method For Manufacturing Asymmetric Devices
- 14 Dec 2012
- JP
- 5153121
Structure And Method For Reducing Miller Capacitance In Field Effect Transistors
- 31 Jul 2012
- US
- 8232151
Structure And Method For Manufacturing Asymmetric Devices
- 27 Dec 2011
- US
- 8084788
%i2p% Method Of Forming Source And Drain Of A Field-effect-transistor And Structure Thereof
- 11 Oct 2011
- US
- 8034692
Structure And Method For Manufacturing Asymmetric Devices

Top collaborators

Hasan M Nayfeh

Title

Bio

Publications

Channel strain engineering for high performance CMOS technology

(110) Channel, SiON gate-dielectric PMOS with record high I_on=1 mA/μm through channel stress and source drain external resistance (R _ext) engineering

Hole transport in nanoscale p-type MOSFET SOI devices with high strain

High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography

Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths

Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakage

Impact of ion implantation damage and thermal budget on mobility enhancement in strained-Si N-channel MOSFETs

Investigation of Scaling Methodology for Strained Si n-MOSFETs Using a Calibrated Transport Model

Patents

Semiconductor Structure And Method Of Making Same

Butted Soi Junction Isolation Structures And Devices And Method Of Fabrication

Replacement Metal Gate Structure And Methods Of Manufacture

Fast - Butted Soi Junction Isolation Structures And Devices And Method Of Fabrication

Method Of Creating Asymmetric Field-effect-transistors

Structure And Method For Manufacturing Asymmetric Devices

Structure And Method For Reducing Miller Capacitance In Field Effect Transistors

Structure And Method For Manufacturing Asymmetric Devices

%i2p% Method Of Forming Source And Drain Of A Field-effect-transistor And Structure Thereof

Structure And Method For Manufacturing Asymmetric Devices

Top collaborators

Lev S Bishop

Petar Jurcevic

Toshinari Itoko

Emily Pritchett