Hemanth Jagannathan

Overview

Title

IBM Distinguished Engineer - Chiplet and Advanced Packaging Technology & Quantum 300mm Scale-out

Location

IBM Research - Albany Albany, NY USA

Bio

Hemanth Jagannathan is a Distinguished Engineer at IBM. He has driven key technical advancements over several generations of semiconductor technologies ranging from planar, FinFET to Nanosheet and beyond nanosheet device architectures. Hemanth is currently the technical executive responsible for Chiplet and Advanced Packaging Technology at IBM Research. He received his Ph.D. in Electrical Engineering from Stanford University and began his technical career at IBM working on high-k metal gate technology. He drove multiple innovations on novel gate stack materials and processes that are being used to this day in advanced CMOS logic technologies. Hemanth also led the advanced semiconductor FEOL process technology team and was responsible in defining the comprehensive semiconductor process strategy for beyond planar, FinFET, Nanosheet and future device architectures. He was the Hardware Technologist who spearheaded the innovations for the Vertical-Transport Nanosheet Field Effect Transistor (VTFET) program at IBM.

Hemanth serves as an IBM representative in multiple academic engagements across the US. He is the executive director for the SUNY-IBM Artificial Intelligence Collaborative Research Alliance where he oversees joint AI research ranging from hardware, algorithms to software and applications. Hemanth is the recipient of multiple IBM Outstanding Technical Achievement Awards and Research Division Awards for his technical accomplishments. He is a senior member at IEEE and has authored/co-authored over 100 technical publications and holds over 200 patents in the semiconductor area.

Publications

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Circuits 2011
Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- CSTIC 2011
Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications
- - Kingsuk Maitra
  - Ali Khakifirooz
  - et al.
- 2011
- IEEE Electron Device Letters
Measurement of oxygen diffusion in nanometer scale HfO₂ gate dielectric films
- - Sufi Zafar
  - Hemanth Jagannathan
  - et al.
- 2011
- Applied Physics Letters
Hot-carrier degradation in undoped-body etsoi fets and soi finfets
- - Miaomiao Wang
  - Pranita Kulkarni
  - et al.
- 2010
- IRPS 2010
A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- - Veeraraghvan S. Basker
  - Theodorus E. Standaert
  - et al.
- 2010
- VLSI Technology 2010
Extraction of effective oxide thickness for SOI FINFETs with high-κ/Metal gates using the body effect
- - Sujata Paul
  - Frank Yeh
  - et al.
- 2010
- IEEE Electron Device Letters
Optimizing band-edge high-κ/metal gate n-MOSFETs with ALD lanthanum oxide cap layers-oxidant and positioning effects
- - Robert D. Clark
  - H. Jagannathan
  - et al.
- 2010
- ECS Transactions
Methodology of ALD HfO₂ high-κ gate dielectric optimization by cyclic depositions and anneals
- - H. Jagannathan
  - Robert D. Clark
  - et al.
- 2010
- ECS Transactions
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- - H. Kawasaki
  - V.S. Basker
  - et al.
- 2009
- IEDM 2009

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Patents

- 26 Sep 2023
- JP
- 7356982
Replacement Metal Gate Process For Vertical Transport Field-effect Transistor
- 14 Sep 2023
- CN
- ZL201880081159.7
Formation Of Self-aligned Bottom Spacer For Vertical Transistors
- 28 Aug 2023
- US
- 11742246
Local Isolation Of Source/drain For Reducing Parasitic Capacitance In Vertical Field Effect Transistors
- 28 Aug 2023
- US
- 11742426
Forming Crossbar And Non-crossbar Transistors On The Same Substrate
- 07 Aug 2023
- CN
- ZL201880033111.9
Bottom Contact Resistance Reduction On Vfet
- 08 May 2023
- US
- 11646373
Vertical Field Effect Transistor With Bottom Spacer
- 19 Apr 2023
- JP
- 7266352
Formation Of Self-aligned Bottom Spacer For Vertical Transistors
- 27 Mar 2023
- US
- 11615990
Cmos Top Source/drain Region Doping And Epitaxial Growth For A Vertical Field Effect Transistor
- 09 Feb 2023
- CN
- ZL201780065359.9
Vertical Transport Fet Devices Utilizing Low Temperature Selective Epitaxy
- 06 Feb 2023
- US
- 11575022
Vertical Field-effect Transistor Late Gate Recess Process With Improved Inter-layer Dielectric Protection

Blog posts

VTFET: The revolutionary new chip architecture that could keep Moore’s Law alive for years to come
News
Brent Anderson and Hemanth Jagannathan
14 Dec 2021
5 minute read

Top collaborators

Hemanth Jagannathan

Overview

Title

Location

Bio

Publications

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell

Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology

Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications

Measurement of oxygen diffusion in nanometer scale HfO₂ gate dielectric films

Hot-carrier degradation in undoped-body etsoi fets and soi finfets

A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

Extraction of effective oxide thickness for SOI FINFETs with high-κ/Metal gates using the body effect

Optimizing band-edge high-κ/metal gate n-MOSFETs with ALD lanthanum oxide cap layers-oxidant and positioning effects

Methodology of ALD HfO₂ high-κ gate dielectric optimization by cyclic depositions and anneals

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Patents

Replacement Metal Gate Process For Vertical Transport Field-effect Transistor

Formation Of Self-aligned Bottom Spacer For Vertical Transistors

Local Isolation Of Source/drain For Reducing Parasitic Capacitance In Vertical Field Effect Transistors

Forming Crossbar And Non-crossbar Transistors On The Same Substrate

Bottom Contact Resistance Reduction On Vfet

Vertical Field Effect Transistor With Bottom Spacer

Formation Of Self-aligned Bottom Spacer For Vertical Transistors

Cmos Top Source/drain Region Doping And Epitaxial Growth For A Vertical Field Effect Transistor

Vertical Transport Fet Devices Utilizing Low Temperature Selective Epitaxy

Vertical Field-effect Transistor Late Gate Recess Process With Improved Inter-layer Dielectric Protection

Blog posts

VTFET: The revolutionary new chip architecture that could keep Moore’s Law alive for years to come

Top collaborators

Dechao Guo

Huiming Bu

Nicolas Loubet

Brent Anderson