Chiplet and Packaging
Building new architectures for next-generation AI.
Overview
IBM offers chiplet and advanced packaging technology capabilities to supercharge innovations for AI and logic. By bringing multiple technologies together at the package level to increase performance and reduce cost, our frameworks provide a new paradigm for semiconductor innovations as well as a new pathway to meet AI’s increasing performance demands. Our recent breakthroughs in packaging R&D include the novel use of infrared laser debonding with silicon handler wafers, which offers new capabilities compared to the industry standard of glass carrier wafers. We’re also pioneering a new hybrid bonding approach that drastically reduces the I/O interconnection size needed between two chiplets, paving the way for new designs. Our packaging facility in Bromont, Canada manufactures 100,000 advanced flip chip modules each week. As the largest Outsourced Semiconductor Assembly and Test facility in North America, its mission is to transform semiconductor components into state-of-the-art microelectronic solutions.
Our work
- ExplainerMike Murphy
IBM Research unveils hybrid bonding for packaging chips
NewsMike MurphyThe path to 1 nanometer chips and beyond
ResearchMike MurphyThe future of computer chips is being built in Albany
Deep DiveMike MurphyThe breakthrough that could simplify the 3D chipmaking supply chain
NewsDale McHerron
Publications
Effective Media Approximation in Investigating Heat Transfer through Multiple Sandwiched Layers of BEOL Materials
- Amogh Wasti
- Zongmin Yang
- et al.
- 2025
- SHTC 2025
Innovative BEOL Oxide-Based Devices as Key Enablers for High-Performing Heterogeneous Systems
- 2025
- DRC 2025
A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications
- 2025
- ISCA 2025
IBM’s SARA SoC/SiP Project: Application-Driven High Level View
- Pradip Bose
- 2025
- ISCA 2025
Chiplet and Heterogeneous integration Technologies for HPC and AI
- 2025
- VLSI Technology and Circuits 2025
Architectural Benchmarking of Compute-in-Memory Systems
- Pritish Narayanan
- Sidney Tsai
- 2025
- VLSI Technology and Circuits 2025