Huiming Bu

Title

Vice President: IBM Semiconductors Global R&D and Albany Operations

Bio

Dr. Huiming Bu is responsible for IBM global Semiconductor R&D strategy across world-wide labs. He oversees R&D activities in advanced logic, chiplet and advanced packaging, emerging memory and analog AI hardware at IBM Research. In addition to leading semiconductor technology R&D agenda, Huiming is also responsible for IBM Research Albany Lab site and fab operations.

Huiming has ~20 years of professional experience in semiconductor technology R&D at IBM after he received his Ph.D. in Electrical Engineering from Yale University. Huiming has authored/co-authored 100+ technical publications and holds 100+ patents in semiconductor domain.

Huiming started his technical career at IBM on High-κ/Metal Gate project and then led SOI FinFET research and early development for IBM’s 14nm node technology. After that, Huiming and his team delivered 10nm/7nm technology R&D for IBM and its Joint Development Alliance (JDA) partners. They are now working on 2nm development and 1nm & beyond pathfinding R&D. Recently, as IBM formed Semiconductors division under IBM Research, the footprint has expanded from advanced logic to chiplet & advanced packaging, intelligent fab, cloud based EDA and design.

Publications

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
- - K. Cheng
  - A. Khakifirooz
  - et al.
- 2009
- IEDM 2009
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
- - K. Cheng
  - A. Khakifirooz
  - et al.
- 2009
- VLSI Technology 2009
Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances
- - Elbert Huang
  - Eric Joseph
  - et al.
- 2008
- IEEE International SOI Conference 2008
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- - K. Henson
  - H. Bu
  - et al.
- 2008
- IEDM 2008
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- - M. Chudzik
  - B. Doris
  - et al.
- 2007
- VLSI Technology 2007

Patents

- 10 Aug 2020
- US
- 10741647
Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices
- 10 Aug 2020
- US
- 10741544
Integration Of Electrostatic Discharge Protection Into Vertical Fin Technology
- 15 Jun 2020
- US
- 10685866
Fin Isolation To Mitigate Local Layout Effects
- 18 May 2020
- US
- 10658224
Fin Oxidation By Flowable Oxide Fill And Steam Anneal To Mitigate Local Layout Effects
- 24 Feb 2020
- US
- 10573727
Vertical Transistor Device
- 30 Dec 2019
- US
- 10522636
Fin Field-effect Transistor For Input/output Device Integrated With Nanosheet Field-effect Transistor
- 16 Dec 2019
- US
- 10510892
Forming A Sacrificial Liner For Dual Channel Devices
- 09 Dec 2019
- US
- 10504889
Integrating A Junction Field Effect Transistor Into A Vertical Field Effect Transistor
- 21 Oct 2019
- US
- 10453922
Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices
- 16 Sep 2019
- US
- 10418462
Silicidation Of Bottom Source/drain Sheet Using Pinch-off Sacrificial Spacer Process

Top collaborators

Huiming Bu

Title

Bio

Publications

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Patents

Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices

Integration Of Electrostatic Discharge Protection Into Vertical Fin Technology

Fin Isolation To Mitigate Local Layout Effects

Fin Oxidation By Flowable Oxide Fill And Steam Anneal To Mitigate Local Layout Effects

Vertical Transistor Device

Fin Field-effect Transistor For Input/output Device Integrated With Nanosheet Field-effect Transistor

Forming A Sacrificial Liner For Dual Channel Devices

Integrating A Junction Field Effect Transistor Into A Vertical Field Effect Transistor

Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices

Silicidation Of Bottom Source/drain Sheet Using Pinch-off Sacrificial Spacer Process

Top collaborators

Dechao Guo

Dan J. Dechene

Hemanth Jagannathan

Nick Lanzillo