A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET

Abstract

A 300MS/s 12b SAR ADC achieving 61.6dB peak SNDR is presented. It reaches 60.5dB SNDR and 78.7dB SFDR with 0.8Vpp,diff input amplitude at Nyquist. The key elements are a comparator with inverter-based preamplifier and a SAR-based common-mode regulation. The regulation adjusts the common mode on a sample-by-sample basis to improve common-mode rejection. The ADC consumes 7.0mW from a single 0.85V supply, where 3.7mW is contributed by the reference buffer.