Publications

This is our catalog of publications authored by IBM researchers, in collaboration with the global research community. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.

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35 results for Alessandro Cevrero

30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
- - Gain Kim
  - Lukas Kull
  - et al.
- 2019
- ISSCC 2019
6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
- - Alessandro Cevrero
  - Ilter Ozkaya
  - et al.
- 2019
- ISSCC 2019
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET
- - Lukas Kull
  - Danny Luu
  - et al.
- 2018
- ISSCC 2018
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
- - Christian Menoifi
  - Matthias Braendli
  - et al.
- 2018
- ISSCC 2018
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS
- - Ilter Ozkaya
  - Alessandro Cevrero
  - et al.
- 2018
- ISSCC 2018
A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
- - Lukas Kull
  - Danny Luu
  - et al.
- 2017
- ISSCC 2017
A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
- - Alessandro Cevrero
  - Ilter Ozkaya
  - et al.
- 2017
- ISSCC 2017
A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
- - Pier Andrea Francese
  - Matthias Braendli
  - et al.
- 2016
- ISSCC 2016
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
- - Gain Kim
  - Marcel Kossel
  - et al.
- 2020
- IEEE JSSC
A 24-72-GS/s 8-b time-interleaved SAR ADC with 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET
- - Lukas Kull
  - Danny Luu
  - et al.
- 2018
- IEEE JSSC