Montek Singh, Jose A. Tierno, et al.
IEEE Transactions on VLSI Systems
A 6b 10 tap-full rate distributed arithmetic digital finite impulse response filter (DFIR) is reported using dynamic logic datapath with independent precharge and compute signals per domino stage. The basic architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. Two 8b 16-entry loadable tables contain the precomputed partial sums used by the distributed arithmetic algorithms.
Montek Singh, Jose A. Tierno, et al.
IEEE Transactions on VLSI Systems
Hayun Chung, Alexander Rylyakov, et al.
VLSI Circuits 2009
Solomon Assefa, William M. J. Green, et al.
IPC 2012
Azita Emami-Neyestanak, Aida Varzaghani, et al.
VLSI Circuits 2006