Solomon Assefa, William M. J. Green, et al.
OFC 2011
A 6b 10 tap-full rate distributed arithmetic digital finite impulse response filter (DFIR) is reported using dynamic logic datapath with independent precharge and compute signals per domino stage. The basic architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. Two 8b 16-entry loadable tables contain the precomputed partial sums used by the distributed arithmetic algorithms.
Solomon Assefa, William M. J. Green, et al.
OFC 2011
Greg Freeman, Mounir Meghelli, et al.
IEEE Journal of Solid-State Circuits
Behnam Analui, Alexander Rylyakov, et al.
IEEE Journal of Solid-State Circuits
Amol Inamdar, Sergey Rylov, et al.
IEEE TAS