Lukas Kull, Danny Luu, et al.
ISSCC 2017
A decision feedback equalization (DFE) technique suitable for high data-rate I/O link receivers is presented. The technique leverages quarter-rate data slicing to implement a fully speculative 3-tap DFE and uses clock forwarding to reach a speed of 50Gb/s. It corresponds to 20ps timing closure of the most critical path, which is the feedback of the first DFE tap. The RX data-path is implemented in 14nm FinFET CMOS SOI technology. At 0.9V supply the energy-efficiency is 1.6pJ/b when PRBS15 data transmitted at 50Gb/s across a channel with 32.5dB insertion loss are recovered with >30% horizontal margin (BER<10-12).
Lukas Kull, Danny Luu, et al.
ISSCC 2017
Alessandro Cevrero, Ilter Ozkaya, et al.
ISSCC 2019
Ilter Ozkaya, Alessandro Cevrero, et al.
IEEE JSSC
Marcel Kossel, Christian Menolfi, et al.
ESSCIRC 2017