A Disturb Decoupled Column Select 8T SRAM Cell

Abstract

This paper presents a novel 8 transistor SRAM cell that can be used for enhancing cell Vdd<inf>min</inf> at and beyond 90nm technology nodes. This cell provides a way to eliminate the column select read disturb scenario in SRAMs which is one of the impediments to lowering cell voltage. Read disturbs to the selected cell are then minimized by relying on a sense-amp based array architecture which enables discharging the bit-line (BL) capacitance to GND during a read operation thereby enhancing its low voltage operability. The sensitivity of the cell to BL height and sense timing has been studied and the feasibility of the cell has been proved by fabricating a 32Kb array in a 90nm PD/SOI technology. Hardware experiments and simulation results show improvements of cell Vdd<inf>min</inf> over traditional 6T cells by more than 150mV for 90nm PD/SOI technology.