Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window

In this work, we applied the asymmetric double-gate concept to decouple the tradeoff between ferroelectric (FE) thickness (tFE) scaling and memory window (MW) reduction in ferroelectric FET (FeFET). We demonstrate that: i) separating read and write gates and adopting a thick non-FE dielectric gate used for reading can amplify the read MW due to electrostatic coupling between the two gates; ii) a compact model for double-gate FeFET has been demonstrated and calibrated with the experimentally measured switching dynamics; iii) with the calibrated model, design space for a scaled tFE (3nm) and logic-compatible write voltage (1.8V) is identified, offering a possible option for tFE scaling.