A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers

Abstract

This paper presents a novel digital decision feedback equalizer (DFE) design that can relax the feedback timing constraints for analog-to-digital converter (ADC)-based high-speed wireline receivers. The proposed technique breaks the loop-unrolled DFE (LU-DFE) chain by computing multiple LU-DFE chains in parallel with all possible seed symbols, and selecting the appropriate output by the post-processing selection logic. The proposed loop-break DFE (LB-DFE) is functionally equivalent to the conventional DFE with any other implementation techniques such as LU-DFE, look-ahead DFE (LA-DFE), or direct DFE. With topographical synthesis in 28nm CMOS process, the proposed LB-DFE achieved up to 54% of DFE area saving as compared to LA-DFE with look-ahead factor (LF) of 16 for 112Gb/s PAM-4 with 875MHz DSP clock speed. The implementation feasibility and functionality are verified using ZCU111 RFSoC platform at 6Gb/s (3GS/s ADC conversion rate) with a channel exhibiting 25dB loss at 1.5GHz, demonstrating the same bit error rate (BER) performance between the LB-DFE and the LA-DFE. Equipment-based measurements using arbitrary waveform generator (AWG) and real-time oscilloscope transmitting/receiving 40GBaud PAM-4 (80Gb/s) to/from the differential cables with software 21-tap feed-forward equalizer (FFE) and LB-DFE on PC was also conducted.