A self-aligned inverse-T gate fully overlapped LDD device for sub-half micron CMOS

A novel self-aligned technique for fabricating inverse-T gate fully overlapped LDD (FOLD) MOSFETs is proposed. The technique uses an oxide or TiN buffer layer sandwiched in a polysilicon gate stack to act as an RIE (reactive ion etching) etch stop. Both the oxide and TiN exhibit good etch selectivities with respect to polysilicon. Therefore, a controllable, uniform polysilicon finger can be obtained to form the inverse-T structure. A 0.35-μm n-channel inverse-T gate MOSFET with fully overlapped LDD (lightly doped drain) design has been fabricated and characterized. It is found that the inverse-T LDD device preserves the performance of a non-LDD device while providing reliability improvement similar to that of a conventional LDD device. The inverse-T LDD device is suitable for high-performance, high-reliability sub-half-micron device applications.