A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
Publications
Date
Featured collections
Popular topics
56 results for M. Wordeman
First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications
- H. Wu
- V. Katragadda
- et al.
- 2021
- IEDM 2021
Thermo-Compression Bonding and Mass Reflow Assembly Processes of 3D Logic Die Stacks
- Pascale Gagnon
- Christian Bergeron
- et al.
- 2017
- ECTC 2017
A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias
- Matt Wordeman
- Joel Silberman
- et al.
- 2012
- ISSCC 2012
1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
220 mm2 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
- T. Kirihata
- M. Gall
- et al.
- 1998
- ISSCC 1998
Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing
- G. Shahidi
- B. Davari
- et al.
- 1990
- IEDM 1990
A comparative study of hot-carrier instabilities in p- and n-type poly gate MOSFETs
- C.C.-H. Hsu
- D.S. Wen
- et al.
- 1989
- IEDM 1989
A self-aligned inverse-T gate fully overlapped LDD device for sub-half micron CMOS
- D.S. Wen
- C.C.-H. Hsu
- et al.
- 1989
- IEDM 1989
EXPERIMENTAL TECHNOLOGY AND CHARACTERIZATION OF SELF-ALIGNED 0. 1 mu M-GATE-LENGTH LOW-TEMPERATURE OPERATION NMOS DEVICES.
- G.A. Sai-Halasz
- M.R. Wordeman
- et al.
- 1986
- IEDM 1986