A Substrate-Plate Trench-Capacitor (SPT) Memory Cell for Dynamic RAM's

Abstract

A new DRAM cell using a trench capacitor with a grounded substrate plate has been demonstrated with fabrication of functional fully decoded 64K arrays. The cell array is located inside the well and the trench capacitor extends from the planar surface through the well and epitaxial layer into the heavily doped substrate. The polysilicon inside the trench, connected to the source region of the transfer device, is used as the storage node and the bulk silicon surrounding the trench serves as the capacitor-plate electrode. The cell features small area, high capacitance, small leakage current, low soft error rate, reduced surface topography, and a very stable capacitor-plate electrode. The arrays were fabricated in an advanced, 3.3-V, n-well epitaxial CMOS technology with a 15-nm gate insulator. N- and p-channel transistors exhibit transconductances of 120 and 60 mS/mm, respectively, at effective channel lengths of 0.6 µm. Ring oscillators designed at this length have delays of 170 ps at 3.3 V. Copyright © 1986 by the Institute of Electrical and Electronics Engineers, Inc.