Yuan Taur, D.S. Zicherman, et al.
IEEE Electron Device Letters
A six-mask 1-μm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p+ substrate and a retrograde n-well. Self-aligned TiSi2 is formed on n+ and p+ diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n+ poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V. Copyright © 1985 by The Institute of Electrical and Electronics Engineers, Inc.
Yuan Taur, D.S. Zicherman, et al.
IEEE Electron Device Letters
Hu H. Chao, Robert H. Dennard, et al.
IEEE Journal of Solid-State Circuits
Bijan Davari, Robert H. Dennard, et al.
Proceedings of the IEEE
David J. Frank, Yuan Taur
Solid-State Electronics