Marcel Kossel, Thomas Toifl, et al.
IEEE JSSC
An 8-bit digital intensive time-based ADC implemented in 5-nm CMOS is presented in this letter. It proposes a bipolar ramp-based voltage-to-time converter (BVTC) to eliminate the reference voltage and to allow a wide input swing of 0.75 Vpp,diff. A redundancy scheme for the input polarity decision taken for 1-bit voltage domain folding is introduced against wrong decisions which eliminates comparator calibration in analog domain and allows a more efficient design. Sense amplifier latch (SAL) interpolation technique is presented which reduces the power and area consumption when phase interpolating the time-to-digital converter (TDC) signals. The ADC reaches 1 GS/s sampling rate with 0.7-V supply and 1.25 GS/s with 0.8-V supply and achieves 16.6 and 20.3 fJ/conv-step Walden FoM, respectively. The total active area is 313μ m2.
Marcel Kossel, Thomas Toifl, et al.
IEEE JSSC
Daniel Schmidt
PMI Symposium 2025
Rémy Cochereau, Viviana Maffeis, et al.
Advanced Functional Materials
Lukas Kull, Thomas Toifl, et al.
ISSCC 2013