Brain-inspired memory architecture for sparse nonlocal and unstructured workloads

This paper presents a brain-inspired von Neumann memory architecture for sparse, nonlocal, and unstructured workloads. Memory at each node contains selectable windows for optimistic shared access. A low-latency multiple access control for various policies is provided inside the local memory controller, using conditional deferred queuing with shared address list entries and associated lock bits. When combined with a memory-side cache, the proposed architecture is expected to transparently accelerate and flexibly scale the performance of sparse, nonlocal, and unstructured workloads by better regulating the data-access pipelining across local and remote memory requests.