Conference paper
Scaling MPI to short-memory MPPs such as BG/L
M. Farreras, T. Cortes, et al.
ICS 2006
System-on-a-chip technology allows a level of integration that can be leveraged to develop inexpensive high-performance, low-power computing nodes. When used in aggregate, this approach promises to challenge conventional supercomputer architectures in the high-performance computing arena. Systems under consideration reach into the hundreds of thousand nodes per machine. Architecture for these systems are described.
M. Farreras, T. Cortes, et al.
ICS 2006
G. Almasi, D. Hale, et al.
Concurrency: Practice and Experience
D. Beece, J. Goren, et al.
ICCD 1985
N.R. Adiga, G. Almasi, et al.
ACM/IEEE SC 2002