Characterization, Modeling and Extraction of Cu Wire Resistance for 65 nm Technology

Abstract

We present an innovative and comprehensive approach to characterize and model interconnect wire resistance. We have measured Cu wire resistance for fully processed 10 BEOL Cu levels in IBM high performance 65 nm technologies, and analyzed resistance data for multiple wire widths at multiple temperatures. Combined with the SEM cross-section data of a few measured Cu wire structures, we have successfully extracted all parameters of a Spice model for the 65 nm node interconnect resistance. The extracted Spice wire resistance model includes the congregated effects of surface scattering, grain boundary scattering and surface roughness in IBM 65 nm BEOL technology. New behavior of wire resistance is reported for the first time.