Conference paperHigh-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delayM. Hargrove, S.W. Crowder, et al.IEDM 1998
Conference paperCoupling analysis of through-silicon via (TSV) arrays in silicon interposers for 3D systemsBiancun Xie, Madhavan Swaminathan, et al.EMC 2011
PaperThermally Developable, Positive Resist Systems with High SensitivityHiroshi Ito, Reinhold SchwalmJES
PaperCurrent saturation in submicrometer graphene transistors with thin gate dielectric: Experiment, simulation, and theoryShu-Jen Han, Dharmendar Reddy, et al.ACS Nano