Chip package interaction evaluation for a high performance 65nm and 45nm CMOS technology in a stacked die package with C4 and wirebond interconnections

Abstract

An evaluation of 65nm and 45nm CMOS Technology in a stacked die package is presented. The technology uses SiCOH advanced low K and ultra low K back end of line (BEOL) for high performance. A BEOL specific test vehicle was fabricated in these technologies and both flip chip and wirebond die used in a stacked die configuration. Manufacturability evaluations for bond and assembly processes and materials were performed and reliability studies completed on assembled modules. Results will show that the technologies are reliable in this packaging configuration. © 2008 IEEE.