Chip package interaction evaluation for a high performance 65nm and 45nm CMOS technology in a stacked die package with C4 and wirebond interconnections
- Christopher Muzzy
- David Danovitch
- et al.
- 2008
- ECTC 2008
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8 results for J. Wright
The projection of the incidence of dielectric cracking during chip joining with lead free solder bumps
- Thomas M. Shaw
- Xiao Hu Liu
- et al.
- 2016
- IRPS 2016
The strength of BEOL structures fabricated using low K materials and its impact on CPI failures
- Thomas M. Shaw
- Xiao Hu Liu
- et al.
- 2015
- IIRW 2015
Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology
- D. Edelstein
- C.R. Davis
- et al.
- 2004
- IITC 2004
Chip-to-Package Interaction for a 90 nm Cu / PECVD Low-k technology
- W. Landers
- D. Edelstein
- et al.
- 2004
- IITC 2004
90 nm SiCOH technology in 300 mm manufacturing
- L. Clevenger
- M. Yoon
- et al.
- 2004
- ADMETA 2004
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
- D. Edelstein
- H.S. Rathore
- et al.
- 2004
- IRPS 2004
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
- D. Edelstein
- H.S. Rathore
- et al.
- 2004
- IRPS 2004