Deep submicron silicon devices: Materials and processing issues

Abstract

Material and processing challenges in the sub-0.5μm CMOS and bipolar silicon devices will be discussed. New device designs and process have been reported, aimed at addressing the issues of high electric fields and high current densities. For both CMOS and bipolar in the deep-submicron regime, primary considerations will be to maximize the gain in performance, yet concomitantly meet the increasingly stringent reliability requirements.