Digital SNN in 5 nm FinFET CMOS with latency-reducing hybrid spiking scheme operated at 2.6 GHz

A spiking neural network (SNN) in 5 nm FinFET CMOS operated at a spike rate of 2.6 GHz is presented. It uses a hybrid spiking scheme in which the data transmission between neurons is coded jointly in time and code domain, enabling a substantial latency reduction. Compared to a spiking scheme where a single spike is transmitted using a range of 64 time steps (6b resolution), the proposed hybrid scheme is designed to achieve a 16-fold latency reduction, resulting in only 4 time steps applied to a 4b binary-encoded spike bus $(4x2^4=64)$. This extension of the classical, purely time-coded spiking to the proposed hybrid spiking in the time and code domain is motivated by improving the energy efficiency (E=PxDelta_t)$ where pure time coding is disadvantageous because the latency Delta_t is proportional to the code range of the input features. The proposed hybrid spiking scheme breaks this relationship and thus contributes to improving the energy efficiency. Key performance metrics of the experimental SNN chip include an energy efficiency of 1.15 pJ/SOP and a minimum response time of 1.5 ns.