Evaluation of Cu wiring in a production 64 Mb DRAM
W. Cote, G. Costrini, et al.
VLSI Technology 1998
Grain growth of Cu interconnects in a low-k dielectric was achieved at an elevated anneal temperature of 300 °C without stress-migration-related reliability problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional anneal process at 100 °C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects. © 2012 IEEE.
W. Cote, G. Costrini, et al.
VLSI Technology 1998
Ernest Y. Wu, B. Li, et al.
IEDM 2013
C.-C. Yang, F. Baumann, et al.
Microelectronic Engineering
F. Chen, J. Gill, et al.
Microelectronics Reliability