Conference paper
Lower-k SiCOH integration for 65 nm ground rules
T. Nogami, S. Lane, et al.
VMIC 2005
Grain growth of Cu interconnects in a low-k dielectric was achieved at an elevated anneal temperature of 300 °C without stress-migration-related reliability problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional anneal process at 100 °C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects. © 2012 IEEE.
T. Nogami, S. Lane, et al.
VMIC 2005
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ECS Meeting 2011