John G. Long, Peter C. Searson, et al.
JES
The experimentally observed VT roll-off and Drain Induced Barrier Lowering (DIBL) at channel lengths of approximately=0.2 μ m in Si-MOSFETs is underestimated by conventional 2D numerical simulations. In this paper it is shown that this is due to B segregation from the channel region towards the As-implanted source/drain regions during the As activation anneal. The resulting B depletion close to the source and drain lowers the local VT and contributes significantly (up to 50% in 0.2 μ m n-channel MOSFETs) to the VT roll-off and DIBL in sub-quarter micron NMOSFETs. This B redistribution originates mainly from ion implantation damage in the source and drain.
John G. Long, Peter C. Searson, et al.
JES
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
M.E. Mierzwinski, J.D. Plummer, et al.
IEDM 1992
E. Burstein
Ferroelectrics