1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
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50 results for B. Davari
Scalability of SOI technology into 0.13 μm 1.2 V CMOS generation
- E. Leobandung
- M. Sherony
- et al.
- 1998
- IEDM 1998
7.9/5.5 psec room/low temperature SOI CMOS
- F. Assaderaghi
- W. Rausch
- et al.
- 1997
- IEDM 1997
Trade-offs in the integration of high performance devices with trench capacitor DRAM
- S.W. Crowder
- S. Stiffler
- et al.
- 1997
- IEDM 1997
CMOS TECHNOLOGY SCALING, O.lpm AND BEYOND
- Bijan Davari
- 1996
- IEDM 1996
A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology
- S. Subbanna
- P. Agnello
- et al.
- 1996
- IEDM 1996
Effect of the back gate conduction on 0.25 μm SOI devices
- J.L. Pelloie
- D.K. Sadana
- et al.
- 1994
- IEDM 1994
SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993
A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic
- S. Subbanna
- D.L. Harame
- et al.
- 1993
- IEDM 1993
Enhanced short-channel effects in NMOSFETs due to boron redistribution induced by arsenic source and drain implant
- D.K. Sadana
- A. Acovic
- et al.
- 1992
- IEDM 1992