Arkadiy Morgenshtein, Alexander Fish, et al.
IEEE Transactions on VLSI Systems
GDI (Gate Diffusion Input) - a new technique of low power digital circuit design is described. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various PTL design techniques is presented, with respect to the layout area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI as compared to other methods. A variety of logic gates have been implemented in 0.35μm technology to compare the GDI technique with CMOS and PTL. A prototype test chip of 8-bit CLA Adder has been fabricated, based on GDI and CMOS cell libraries, showing up to 45% reduction in power-delay product in GDI. Properties of implemented circuits are discussed, simulation results are reported and measurements of a test chip are presented.
Arkadiy Morgenshtein, Alexander Fish, et al.
IEEE Transactions on VLSI Systems
Eliyahu Osherovich, Vladimir Yanovki, et al.
International Journal of Robotics Research
Oded Katz, Dan A. Ramon, et al.
IEEE Transactions on VLSI Systems
Michael Moreinis, Arkadiy Morgenshtein, et al.
IEEE Transactions on VLSI Systems