Identifying and Removing Artifacts Formed During FIB TEM Sample Preparation of Semiconductor Devices

For many applications, FIB TEM sample preparation has become the method of choice for rapidly producing sub-50 nm thick, high quality TEM samples of specific, sub-15 nm features. FIB TEM prep is particularly needed in the semiconductor industry where device features are ever shrinking and evolving in 3-dimensions, and the TEM has superseded the SEM for many characterization requirements. However, FIB prep artifacts can destroy the samples being prepared or create features in the sample that are not initially known to be caused by FIB or semiconductor processing. In this paper, multiple examples of FIB TEM sample prep artifacts will be shown from semiconductor applications along with the solutions that were developed to enable artifact free TEM samples to be produced. In one case, insufficient sample grounding caused line conductors to blow-out during full 8” wafer FIB TEM prep. In another case, electron beam irradiation was shown to cause severe alteration of nano-structures and at first there was great confusion about the source of the problem. Finally, a show-stopping artifact was created from S contamination in the FIB load lock which caused irreparable damage in samples and grids containing Cu. The source of S was never located but successive chamber plasma cleans rid S from the FIB chamber and allowed successful FIB prep to continue.