A fast physical constraint generator for timing driven layout
W.K. Luk
DAC 1991
In this paper we consider the problem of optimal wiring of VLSI circuits. The topological placement of the circuit elements (macros) on the chip is assumed to have a special hierarchical structure, i.e., to be a slicing floorplan, represented by a binary (slicing) tree. Instead of the usual objective of minimum wire length, we consider the problem of minimizing the overall area of the wired floorplan. For the case of a single multiterminal net connecting n macros, we obtain a wiring algorithm of complexity O(nd), where d is the depth of the slicing tree. The case of several multiterminal nets is still under investigation. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
W.K. Luk
DAC 1991
W.K. Luk, D.T. Tang, et al.
DAC 1986
M. Tamminen, W.K. Luk, et al.
Acta Informatica
W.K. Luk, Paolo Sipala, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems