Multistack Optimization for Data-Path Chip Layout

Abstract

As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data path. The physical decomposition of a chip into a single data-path stack, and control logic as done in the past is not always feasible. The problem of data-path partitioning, and data-path macro placement is crucial for the floorplanning and physical design of these chips. This paper describes a special multistack structure and optimization techniques to partition, place, and wire the data-path macros in the form of the multistack structure, taking into account the connectivity of all the chip logic (data path, control logic, chip drivers, on-chip memory). The overall objective is: 1) to fit the circuits within the chip boundary, 2) to ensure data-path internal wirability, as well as external stack wirability to the other circuits, and 3) to minimize wire lengths for wirability and timing. A tool for automatic multistack optimization has been implemented and applied successfully to layout high density data path chips. © 1991 IEEE