Paul Gond-Charton, Sebastien Gouin, et al.
ECTC 2023
This work advances the current understanding and performance assessment of chiplet interfaces by providing a framework for modeling and joint simulation of signal and power integrity of BoW-based die-to-die interconnects with advanced packaging technology. The study covers data rates up to 16 Gbps. This paper presents a circuit-level implementation of the BoW slice that consists of a driver on one chiplet and a receiver on another chiplet. This work compares the performance of various combinations of high-density transmission lines with different line-and-space and wirelengths. It presents configurations of the BoW data lines that have extremely low power dissipation, less than 0.2 pJ/bit at 8 and 16 Gbps.
Paul Gond-Charton, Sebastien Gouin, et al.
ECTC 2023
Corey Liam Lammie, Hadjer Benmeziane, et al.
Nat. Rev. Electr. Eng.
Sidney Tsai
MRS Fall Meeting 2023
Samuele Ruffino, Kumudu Geethan Karunaratne, et al.
DATE 2024