Thermal Characterization of 3-D Stacked Heterogeneous Integration (HI) Package for High-Power Computing Applications
- Aakrati Jain
- Risa Miyazawa
- et al.
- 2023
- ECTC 2023
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48 results for Arvind Kumar
Signal and Power Integrity Design and Analysis for Bunch-of-Wires (BoW) Interface for Chiplet Integration on Advanced Packaging
- Ram Krishna
- Atom O. Watanabe
- et al.
- 2023
- ECTC 2023
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- IEDM 2005
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- J. Cai
- K. Rim
- et al.
- 2004
- IEDM 2004
Simulation of quantum electronic transport in small devices: A Master equation approach
- M.V. Fischetti
- S.E. Laux
- et al.
- 2003
- IEDM 2003
QDAME simulation of 7.5 nm double-gate Si nFETs with differing access geometries
- S.E. Laux
- A. Kumar
- et al.
- 2002
- IEDM 2002
Gate length and performance scaling of undoped-body extremely thin SOI MOSFETs
- Amlan Majumdar
- Xinlin Wang
- et al.
- 2009
- IEEE Electron Device Letters
Strained-Si channel super-self-aligned back-gate/double-gate planar transistors
- Hao Lin
- Haitao Liu
- et al.
- 2007
- IEEE Electron Device Letters