Solder-Reflowable, High-Throughput Fiber Assembly Achieved by Partitioning of Adhesive Functions

Abstract

Cost-efficient packaging of silicon photonic chips is a key challenge to large scale deployment of silicon photonic devices. We have previously demonstrated a parallelized fiber-to-chip assembly process making use of off-the-shelf fiber components and compatible with standard, automated, high-throughput pick -and-place tools. Here, we show solder-reflow compatibility up to 260°C, negligible optical loss penalty at an extended operating temperature of up to 150°C, and fast adhesive tack times for compatibility with high-throughput tooling. This is achieved by partitioning of adhesive functions across the various critical regions of the assembly.