Amlan Ghosh, Rahul M. Rao, et al.
VLSID 2008
Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45nm PD/SOI technology show a 103 X} reduction in the Write-failure probability with the proposed method. © 2006 IEEE.
Amlan Ghosh, Rahul M. Rao, et al.
VLSID 2008
Rahul M. Rao, Jeffrey L. Burns, et al.
ESSCIRC 2003
Amlan Ghosh, Rahul M. Rao, et al.
ISQED 2008
Rahul M. Rao, Jeffrey L. Burns, et al.
ISLPED 2003