A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
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7 results for R.P. Havreluk
An 18 ns 56-bit multiply-adder circuit
- Robert K. Montoye
- P.W. Cook
- et al.
- 1990
- ISSCC 1990
A High-Speed 128Kbit MRAM Core for Future Universal Memory Applications
- A. Bette
- J.K. DeBrosse
- et al.
- 2003
- VLSI Circuits 2003
On the Removal of Insulator Process Induced Radiation Damage from Insulated Gate Field Effect Transistors at Elevated Pressure
- A. Reisman
- J.M. Aitken
- et al.
- 2019
- JES
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
A High-Speed 128-kb MRAM Core for Future Universal Memory Applications
- John DeBrosse
- Dietmar Gogl
- et al.
- 2004
- IEEE Journal of Solid-State Circuits
TA-A3 Retention Time Studies in Buried-Channel MOSFET Dynamic-Memory Devices
- H.H. Chao
- R.P. Havreluk
- 1980
- IEEE T-ED