Design considerations for 50G+ backplane links
- Thomas Toifl
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
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35 results for Alessandro Cevrero
A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
- 2016
- ISSCC 2016
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
- Alessandro Cevrero
- Cosimo Aprile
- et al.
- 2015
- VLSI Circuits 2015
Adaptive optical interconnects: The ADDAPT project
- Ronny Henker
- J. Pliva
- et al.
- 2015
- SPIE Optics + Photonics 2015
A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth
- Pier Andrea Francese
- Thomas Toifl
- et al.
- 2013
- A-SSCC 2013