Publications

This is our catalog of publications authored by IBM researchers, in collaboration with the global research community. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.

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27 results for Michael P. Beakes

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14-nm CMOS
- - Zeynep Toprak-Deniz
  - Jonathan E. Proesel
  - et al.
- 2020
- IEEE JSSC
A 1.8 pJ/bit 16 × 16Gb/s source-synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- - Timothy O. Dickson
  - Yong Liu
  - et al.
- 2016
- IEEE JSSC
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks
- - Alexander V. Rylyakov
  - Jonathan E. Proesel
  - et al.
- 2015
- IEEE JSSC
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- - Timothy O. Dickson
  - Yong Liu
  - et al.
- 2015
- IEEE JSSC
Multi-Wavelength Optical Transceivers Integrated on Node (MOTION)
- - Daniel M. Kuchta
  - Jonathan E. Proesel
  - et al.
- 2019
- OFC 2019
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os
- - Thomas Toifl
  - Peter Buchmann
  - et al.
- 2014
- ESSCIRC 2014
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS
- - Jean-Olivier Plouchart
  - Mihai Sanduleanu
  - et al.
- 2012
- CICC 2012
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
- - Jean-Olivier Plouchart
  - Mark A. Ferriss
  - et al.
- 2012
- CICC 2012
High-density silicon carrier transmission line design for chip-to-chip interconnects
- - Xiaoxiong Gu
  - Lavanya Turlapati
  - et al.
- 2011
- EPEPS 2011
An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- - Timothy O. Dickson
  - Yong Liu
  - et al.
- 2011
- VLSI Circuits 2011