Sungjae Lee, J. Johnson, et al.
VLSI Technology 2012
Conference paper
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS
Abstract
A 3.2GS/s two-step subranging ADC is implemented in a 45nm SOI-CMOS technology. The measured ENOB is 4.55b at 1.6GHz. The IIP3 is -1.1dBm. The power consumption is 22mW from a 1.05V voltage supply for a FOM of 290fJ/ conversion-step. The chip occupies an active area of 0.07mm2. © 2012 IEEE.
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