Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- IEDM 2005
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20 results for D.C. La Tulipe
SELF-ALIGNED PROCESSES FOR THE GaAs GATE FET.
- H. Baratte
- D.C. La Tulipe
- et al.
- 1985
- IEDM 1985
New phenomena in coupled transport between 2D and 3D electron-gas layers
- P. Solomon
- P.J. Price
- et al.
- 1989
- Physical Review Letters
Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO2/metal stacks
- V. Narayanan
- K. Maitra
- et al.
- 2006
- IEEE Electron Device Letters
Depletion-Mode GaAs SISFET's By Selective Ion Implantation
- H. Baratte
- Paul M. Solomon
- et al.
- 1987
- IEEE Electron Device Letters
Upside-down FETS
- D.C. La Tulipe Jr.
- D.J. Frank
- et al.
- 2008
- IEEE International SOI Conference 2008
Critical aspects of layer transfer and alignment tolerances for 3D integration processes
- D.C. La Tulipe
- L.T. Shi
- et al.
- 2006
- GBC 2006
Assembly technology for three dimensional integrated circuits
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- VMIC 2005
High resolution 248 nm bilayer resist
- Q. Lin
- K.E. Petrillo
- et al.
- 1999
- SPIE Advances in Resist Technology and Processing 1999
Extension of 248 nm optical lithography: A thin film imaging approach
- Qinghuang Lin
- Ahmad D. Katnani
- et al.
- 1998
- Microlithography 1998