Design considerations for high-density high-speed bipolar ROM
- Pong-Fei Lu
- Hyun J. Shin
- et al.
- 1993
- VLSI-TSA 1993
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25 results for Hyun J. Shin
A 1.2 ns/1 ns 1 K∗16 ECL dual-port cache RAM
- Hyun J. Shin
- P.F. Lu
- et al.
- 1993
- ISSCC 1993
High-Speed Low-Power Darlington ECL Circuit
- C.T. Chuang
- Ken Chin
- et al.
- 1993
- IEEE Journal of Solid-State Circuits
High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage
- C.T. Chuang
- Ken Chin
- et al.
- 1992
- CICC 1992
A 5Gb/s 16×16 Si-bipolar crosspoint switch
- Hyun Shin
- James Warnock
- et al.
- 1992
- ISSCC 1992
High-Speed Low-Power ECL Circuit with AC-Coupled Self-Biased Dynamic Current Source and Active-Pull-Down Emitter-Follower Stage
- C.T. Chuang
- Ken Chin
- et al.
- 1992
- IEEE Journal of Solid-State Circuits
An Experimental 5-Gb/s 16 x 16 Si-Bipolar Crosspoint Switch
- Hyun J. Shin
- Michael J. Immediato
- 1992
- IEEE Journal of Solid-State Circuits
A High-Speed Low-Power JFET Pull-Down ECL Circuit
- Hyun J. Shin
- Pong-F. Lu
- et al.
- 1991
- IEEE Journal of Solid-State Circuits
Full-Swing BiCMOS Logic Circuits with Complementary Emitter-Follower Driver Configuration
- Hyun J. Shin
- 1991
- IEEE Journal of Solid-State Circuits
A high-speed low-power JFET pull-down ECL circuit
- Hyun J. Shin
- P.F. Lu
- et al.
- 1990
- Bipolar Circuits and Technology Meeting 1990