A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
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5 results for J.L. Snare
A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology
- S. Subbanna
- P. Agnello
- et al.
- 1996
- IEDM 1996
High-performance 0.08 μm CMOS
- L. Su
- S. Subbanna
- et al.
- 1996
- VLSI Technology 1996
Modeling the Small-Emitter Effect in Polysilicon-Emitter Transistors
- L. Wagner
- K.M. Kim
- et al.
- 1992
- BCTM 1992
Thickness measurement of ultra-thin gate dielectrics under inversion condition
- W. Zhu
- Mukesh Khare
- et al.
- 2001
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings